The invention relates to integrated circuits.
In certain applications, and charge-coupled devices may be mentioned by way of example, there is a need to produce very narrow electrodes extending in length on either side of an elongate semiconductor zone. This is the case, for example, for anti-dazzle devices associated with photosensitive charge-coupled devices. Two conducting strips are often produced which are isolated from a semiconductor substrate in which charge transfers take place, these strips flanking an elongate doped semiconductor region formed in the substrate: the doped region serves as a drain for the excess charges and the conducting strips serve to create a potential barrier defining the excess level above which charges have to be drained away in order to prevent dazzling.
In the conventional technique, a polycrystalline-silicon layer is deposited in order to make up the electrodes and it is etched in order to define the semiconductor strips; then a doping impurity is implanted in the gap between two polycrystalline-silicon strips in order to make up the drain in the form of an elongate strip. But conventional photolithography techniques do not then enable the total width necessary for producing the whole unit comprising the two conducting strips separated by a doped semiconductor strip to be reduced below approximately 5 micrometers. Now, it would be preferable to reduce this width to a lower value in order to gain space in the integrated circuit.
This is why the invention provides a novel process for forming conducting strips self-aligned with doped semiconductor strips, the whole unit having a very small width.
According to the invention, a manufacturing process is provided comprising the following steps:
a) a masking layer, preferably made from silicon nitride, is deposited onto the surface of a substrate, PA1 b) this layer is etched in order to define at least one non-masked strip; PA1 c) an opening is formed in the substrate at that place where it is not protected by the masking layer, this opening also extending beneath the edges of the masking layer, leaving these edges overhanging above the opening; PA1 d) some polycrystalline silicon matching the contour of the substrate and of the overhanging edges is deposited; PA1 e) the silicon is removed by etching without a mask so that very narrow silicon strips remain essentially only beneath the overhanging edges. PA1 starting with a substrate, at least one thick insulating layer is formed on this substrate (in practice this layer is formed by the localised oxidation step which is in any case necessary for the production of the other circuit elements); PA1 a masking layer is deposited for protecting the thick insulating layer from the etching; PA1 the masking layer is etched in order to define a non-masked strip; PA1 the thick insulating layer is etched over its entire thickness in the masked strip and beneath the edges of the masking layer in order to leave these edges overhanging (etching with so-called underetching); PA1 and the previously indicated process is continued: possible formation of a thin insulating layer in the bared zone; deposition of polycrystalline silicon matching the shape of the opening and reaching beneath the overhangs; uniform etching without a mask in order to remove the entire thickness of the polycrystalline silicon in the middle of the opening in which middle it has been deposited, without removing it from beneath the overhangs.
In other words, the main point of the process according to the invention is the formation of conducting strips, the particular feature of which is that they are located beneath overhanging edges, that is to say their width is defined from the length of overhang of the edges of a masking layer which has served to define an opening in a substrate. The word substrate is taken in the wide sense, as the surface of the substrate can be a semiconductor surface or a semiconductor surface covered with an insulating layer of a certain thickness. And the opening formed in the substrate can be an opening formed in a semiconductor or an opening formed in an insulating layer.
In a particularly advantageous manner, in order to form the opening in the substrate (step c), a localised thick oxidation step (step c1) is used followed by a deoxidation step (step c2). This exploits the fact that thick oxidation steps are provided in any case for other elements of the integrated circuit, but here this step is used in unusual manner since the thick oxide formed is not preserved. The masking layer is then, more precisely, an oxidation-preventing masking layer.
An impurity will be implanted in the substrate if it is desired to define a doped semiconductor region self-aligned with the substrate; depending on the case, this impurity will be implanted before the removal of the thick oxide or after etching of the polycrystalline silicon.
In the case where the two grids adjacent to the doped semiconductor strip have to stay at identical potentials, it is possible to deposit an additional polycrystalline-silicon layer in order to fill the gap between the two grids above the doped semiconductor zone.
In general, the grids will be isolated from the semiconductor substrate by a thin insulating layer formed before deposition of the polycrystalline silicon.
The masking layer can stay or be removed at the end of the manufacturing steps indicated hereinabove.
The etching of the polycrystalline silicon at the end of the process is preferably a vertical anisotropic etching (plasma etching). It is carried out in a uniform manner, that is to say without a mask, at the very least without a mask serving to define the width of the lines to be produced.
In a process variant which is particularly beneficial on account of its compatibility with the manufacture of other circuit elements on the same substrate, the procedure is carried out in the following manner:
The doping of the substrate, in order to define a doped region between the silicon strips, may be carried out before the deposition of the polycrystalline silicon or after etching of the latter.